Patent Filed by Samsung Electronics Co. Ltd. Inventors Detailed Efficient Test Algorithms for Memory Devices

A new patent was published online on October 14, 2025, detailing efficient test algorithms for memory devices. The invention, filed by Samsung Electronics Co. Ltd. inventors Jungmin Bak, Junyoung Ko, and Changhwi Park on February 9, 2023, provides a test device and system for detecting whether an internal command of a memory device is normally generated. This breakthrough has significant implications for the development of reliable memory devices, particularly in the context of using Dynamic Random Access Memory (DRAM) as a last-level cache.

The test device, as described in the patent, includes a power supply circuit, a current sensor, a clock driver, and a test controller. The test controller transmits a command signal to the memory device, measures a first current flowing to the device in a first period of the clock signal, measures a second current in a second period of the clock signal, and determines whether the memory device has a defect based on the comparison of the two currents.

Key Takeaways:

  • The patent describes a test device and system for detecting defects in memory devices using efficient test algorithms.
  • The test device includes a power supply circuit, a current sensor, a clock driver, and a test controller.
  • The test controller measures a first current flowing to the memory device in a first period of the clock signal and a second current in a second period of the clock signal.
  • The patent provides a detailed description of the test algorithms and the test device architecture.
  • The invention has significant implications for the development of reliable memory devices, particularly in the context of using DRAM as a last-level cache.
  • The patent provides 18 claims, including claims for a test device, a method of testing a memory device, and a test system.

Statistics:

  • The patent was filed on February 9, 2023, and published online on October 14, 2025.
  • The patent has 18 claims, including claims for a test device, a method of testing a memory device, and a test system.
  • The test device includes a power supply circuit, a current sensor, a clock driver, and a test controller.
  • The test controller measures a first current flowing to the memory device in a first period of the clock signal and a second current in a second period of the clock signal.

Sources:

  • Bak, Jungmin. "Test devices and systems that utilize efficient test algorithms to evaluate devices under test." U.S. Patent Number 12442842, filed February 9, 2023, and published online on October 14, 2025.
  • https://ppubs.uspto.gov/pubwebapp/external.html?q=(12442842)&db=USPAT&type=ids