Samsung Electronics Co. Ltd. Receives Patent for Vertical Non-Volatile Memory Devices

Strategic Insights -

Samsung Electronics Co. Ltd., a leading electronics manufacturer, has received a patent for a vertical non-volatile memory device that improves the integration of memory devices by stacking cell transistors in a vertical direction.

The inventive concept, according to the patent, provides a vertical non-volatile memory device that includes a memory stack structure with gate lines and interlayer insulating layers alternately stacked in a stacking direction, a channel layer located in a channel hole of the memory stack structure, and an information storage structure including a composite blocking insulating layer, a charge storage layer, and a tunneling insulating layer sequentially arranged in a horizontal direction. The composite blocking insulating layer includes a first metal oxide having a higher dielectric constant than silicon oxide and a second blocking insulating layer having a lower oxidation density than the first blocking insulating layer.

According to the patent claims, the vertical non-volatile memory device includes:

  • A memory stack structure with gate lines and interlayer insulating layers alternately stacked in a stacking direction, with a channel hole formed in the gate lines and interlayer insulating layers to extend in the stacking direction
  • A channel layer located in the channel hole of the memory stack structure, extending in the stacking direction
  • An information storage structure including a composite blocking insulating layer, a charge storage layer, and a tunneling insulating layer sequentially arranged in a horizontal direction from the gate lines to the channel layer

The patent also provides for various embodiments of the vertical non-volatile memory device, including:

  • A composite blocking insulating layer with a first metal oxide having a higher dielectric constant than silicon oxide
  • A second blocking insulating layer having a lower oxidation density than the first blocking insulating layer
  • A plurality of sub-blocking insulating layers
  • A first sub-blocking insulating layer and a second sub-blocking insulating layer that is between the first sub-blocking insulating layer and the charge storage layer and has a lower oxidation density than the first sub-blocking insulating layer

Key Takeaways:

  • The patent provides a method for improving the integration of memory devices by stacking cell transistors in a vertical direction
  • The inventive concept includes a memory stack structure with gate lines and interlayer insulating layers alternately stacked in a stacking direction
  • The channel layer is located in the channel hole of the memory stack structure and extending in the stacking direction
  • The information storage structure includes a composite blocking insulating layer, a charge storage layer, and a tunneling insulating layer sequentially arranged in a horizontal direction from the gate lines to the channel layer
  • The composite blocking insulating layer includes a first metal oxide having a higher dielectric constant than silicon oxide
  • The second blocking insulating layer has a lower oxidation density than the first blocking insulating layer
  • Various embodiments of the vertical non-volatile memory device are provided, including a composite blocking insulating layer with a first metal oxide having a higher dielectric constant than silicon oxide and a plurality of sub-blocking insulating layers

Statistics:

  • The patent was filed on June 27, 2022, and published online on October 14, 2025
  • Patent number 12446221 is assigned to Samsung Electronics Co. Ltd.
  • The inventive concept improves the degree of integration of a memory device by stacking cell transistors in a vertical direction
  • The memory stack structure includes gate lines and interlayer insulating layers alternately stacked in a stacking direction
  • The channel layer is located in the channel hole of the memory stack structure and extending in the stacking direction
  • The information storage structure includes a composite blocking insulating layer, a charge storage layer, and a tunneling insulating layer sequentially arranged in a horizontal direction from the gate lines to the channel layer

Sources:

  • Bae, Minkyung. Vertical non-volatile memory devices. U.S. Patent Number 12446221, filed June 27, 2022, and published online on October 14, 2025. Patent URL (for desktop use only): https://ppubs.uspto.gov/pubwebapp/external.html?q=(12446221)&db=USPAT&type=ids