Cadence Design Systems Announces Philips Semiconductors Adopting SP&R for Enhanced Design Efficiency

Strategic Insights -

Cadence Design Systems, Inc., the world's leading supplier of electronic design products and services, announced that Philips Semiconductors has adopted Cadence SP&R (synthesis/place-and-route) into their qualified design flow. Philips designs a wide variety of ASICs and systems-on-chips (SOCs) and has chosen Cadence SP&R to enhance existing processes and speed design closure in 0.18-micron processes.

Philip's success with Cadence SP&R is a prime example of complete teams of front- and back-end designers enjoying increased productivity due to the tool's complete front-to-back solution that eliminates iterations in comparative flows. During qualification, Cadence's PKS produced single-pass results where Philips previously performed multiple, costly iterations between synthesis and place-and-route.

Key Takeaways:

  • Philips Semiconductors adopted Cadence SP&R into their qualified design flow to enhance existing processes and speed design closure in 0.18-micron processes.
  • Cadence SP&R, consisting of Envisia PKS physical synthesis and Silicon Ensemble PKS optimization place-and-route, provides a complete front-to-back solution that eliminates iterations in comparative flows.
  • Philips benefits from SP&R's single-pass results, achieving tight correlation with final routed results, and eliminating multiple costly iterations between synthesis and place-and-route.
  • Cadence's PKS technology provides tight integration between synthesis, timing, placement, and true global routing engines, resulting in better quality of results.
  • SE-PKS uses Cadence PKS technology to restructure gate-level netlists produced by conventional wireload-model-based synthesis.
  • Philips' adoption of Cadence SP&R demonstrates the company's commitment to leveraging leading-edge design tools to enhance productivity and efficiency.
  • Cadence Envisia PKS physical synthesis and Silicon Ensemble PKS optimization place-and-route are available on UNIX-based workstations from Hewlett-Packard, Sun Microsystems, and AIX-based workstations from IBM.

Statistics:

  • Philips has chosen Cadence SP&R to enhance existing processes and speed design closure in 0.18-micron processes.
  • The company plans to complete its first 0.18-micron production design using SP&R this summer, and plans several more before year's end.
  • Cadence's PKS produced single-pass results, achieving a correlation of PKS results to final routed results within 3 percent to 5 percent.
  • Cadence SP&R's pricing starts at $100,000 for Envisia PKS physical synthesis and $400,000 for Silicon Ensemble PKS optimization place-and-route.

Sources:

  • "Cadence Announces Philips Semiconductors Adopting SP&R for Enhanced Design Efficiency," Business Wire, July 12, 2000.
  • "About Cadence," Cadence Design Systems, Inc., http://www.cadence.com.
  • "Note to Editors," Cadence Design Systems, Inc., July 12, 2000.