Compact D-Band Frequency Multiplier Chain Design Showcases Potential for Next-Generation Wireless Technology

Strategic Insights -

Researchers from the University of California Los Angeles (UCLA) have designed a compact D-band frequency multiplier chain using Taiwan Semiconductor Manufacturing Company Limited (TSMC) 16 nm technology. The new design leverages the high frequency operation of the p-FinFET device, enabling efficient frequency tripling and quadrupling. The innovative design has been peer-reviewed and showcases potential for next-generation wireless technology.

Key Takeaways:

  • The compact D-band frequency multiplier chain occupies a core area of only 0.068mm2, making it an attractive solution for future wireless applications.
  • The design utilizes TSMC 16 nm technology and the p-FinFET device, which offers a unique high f(max) feature that sets the foundations for this design.
  • The frequency multiplier chain consists of an inductor-less active balun, two frequency tripler cells, an interstage amplifier, and a two-stage driving amplifier at the output.
  • The proposed model was applied to find the optimal bias condition when designing the frequency triplers, achieving a conversion gain of 1.6 dB and a P(sat) of -2.8 dBm with 58 mW DC power consumption.
  • The second bias point achieves a higher conversion gain and P-sat at 4.7 and 1.8 dBm with 102 mW DC power consumption.
  • The research uses a time-domain double-clipped piece-wise linear model to analyze the current waveform of the frequency tripler, which proves to be accurate in predicting the harmonic generation behavior of FinFET by comparing with simulation.
  • The proposed design has been measured under two bias conditions, with the first achieving a harmonic rejection ratio of 44 dBc and the second achieving a higher conversion gain and P-sat.

Statistics:

  • The compact D-band frequency multiplier chain occupies a core area of only 0.068mm2, reducing the overall size and power consumption of future wireless systems.
  • The proposed design achieves a conversion gain of 1.6 dB and a P(sat) of -2.8 dBm with 58 mW DC power consumption, making it an efficient solution for future wireless applications.
  • The second bias point achieves a higher conversion gain and P-sat at 4.7 and 1.8 dBm with 102 mW DC power consumption, demonstrating the potential of this design for high-performance wireless systems.

Sources:

  • "Design of a D-band Multiply-by-9 Frequency Multiplier Chain In 16 Nm P-finfet Technology With Waveform Modeling," IEEE Transactions On Terahertz Science and Technology, 2025;15(5):864-876.
  • IEEEXPLORE. IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY. IEEE Institute of Electrical and Electronics Engineers. www.ieee.org/
  • NewsRx. New Technology Study Findings Have Been Reported by Investigators at University of California Los Angeles (UCLA) (Design of a D-band Multiply-by-9 Frequency Multiplier Chain In 16 Nm P-finfet Technology With Waveform Modeling). Journal of Engineering. October 20, 2025; p 2290.