Deep Learning Accelerators: A New Era in Computer-Aided Design

Strategic Insights -

Researchers at Tsinghua University have made groundbreaking advancements in computer-aided design, specifically in the development of deep learning accelerators. According to the study, the convolutional neural network (CNN) has become a top-notch method for various artificial intelligence domains. The researchers proposed a novel compiler, DNNVM, which integrates optimizers for graphs, loops, and data layouts, an assembler, a runtime supporter, and a validation environment. This compiler transforms CNN models into a directed acyclic graph, enabling the optimization of both data layout and pipeline.

Key Takeaways:

  • The convolutional neural network (CNN) has become a state-of-the-art method for several artificial intelligence domains, with increasingly complex models being both computation-bound and I/O-bound.
  • The DNNVM compiler is an integration of optimizers for graphs, loops, and data layouts, an assembler, a runtime supporter, and a validation environment, which transforms CNN models into a directed acyclic graph (XGraph).
  • On the Xilinx ZU2 and ZU9, the researchers achieved equivalently state-of-the-art performance on their benchmarks, with a throughput of 2.82 TOPs/s and an energy efficiency of 123.7 GOPs/s/W for VGG.
  • The study achieved 1.38 TOPs/s for ResNet50 and 1.41 TOPs/s for GoogleNet.
  • Financial supporters for the research include Xilinx, Beijing Innovation Center for Future Chips, Tsinghua Xilinx AI Research Fund, Beijing National Research Center for Information Science and Technology, National Key Research and Development Program of China, National Natural Science Foundation of China, Project of Tsinghua University and Toyota Joint Research Center for AI Technology of Automated Vehicle.
  • The DNNVM compiler was designed to leverage heterogeneous optimizations on FPGA-based CNN accelerators.

Statistics:

  • Median throughput achieved by the researchers: 2.82 TOPs/s on the Xilinx ZU9@330 MHz.
  • Energy efficiency achieved: 123.7 GOPs/s/W on the Xilinx ZU9@330 MHz.
  • TOPs/s achieved for VGG: 2.82.
  • GOPs/s/W achieved for VGG: 123.7.
  • TOPs/s achieved for ResNet50: 1.38.
  • TOPs/s achieved for GoogleNet: 1.41.

Sources:

  • [1] Dnnvm: End-to-end Compiler Leveraging Heterogeneous Optimizations On Fpga-based Cnn Accelerators. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020;39(10):2668-2681.
  • [2] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ieee-Inst Electrical Electronics Engineers Inc, 445 Hoes Lane, Piscataway, NJ 08855-4141, USA.
  • [3] Tsinghua University, Yu Wang, Tsinghua National Laboratory for Information Science and Technology, Beijing 100084, People's Republic of China.