Patent Application for Ramped Interconnect in Semiconductor Fabrication Described

Strategic Insights -

A patent application for a novel ramped interconnect in semiconductor fabrication has been made available online. The inventors, Ming and Samsudin, propose an apparatus, system, and method for providing a ramped interconnect that addresses the limitations of known vertical interconnect access (VIA) techniques. The disclosure describes an electrical interconnection system comprising a first semiconductor substrate, a second semiconductor substrate, a ramp, and a conductive trace formed on the ramp to connect circuits on the two substrates.

Key Takeaways:

  • The inventors, Ming and Samsudin, have filed a patent application for an apparatus, system, and method of providing a ramped interconnect in semiconductor fabrication.
  • The technology aims to address the limitations of known VIA techniques, including difficulties in filling conductive material, roughening of conductive material, and mechanical instability of the conductive material.
  • The proposed system includes a first semiconductor substrate, a second semiconductor substrate, a ramp, and a conductive trace formed on the ramp to electrically connect circuits on the two substrates.
  • The conductive trace may comprise a nanoparticle conductive ink and may have a thickness of between about 10 and about 75 microns.
  • The ramp size may range from about 800 microns to about 1000 microns, and the angle of the ramp may be between about 45° and about 70°.
  • The system may include surface mount technology (SMT) components, and the conductive trace may have a contact resistance in a range of about 0.10 and about 1.50 ohms/sq.
  • The inventors propose using a silver nanoparticle ink that contains about 60 weight/percent bulk silver for the conductive trace.
  • The patent application provides a detailed description of the apparatus, system, and method, claiming 16 specific features, including the use of additively manufactured conductive traces and molded substrates.

Statistics:

  • The patent application was filed on December 18, 2024.
  • The patent application was made available online on October 2, 2025.
  • The inventors propose using nanoparticle conductive ink for the conductive trace.
  • The conductive trace may have a thickness of between about 10 and about 75 microns.
  • The ramp size may range from about 800 microns to about 1000 microns.
  • The angle of the ramp may be between about 45° and about 70°.
  • The system may include surface mount technology (SMT) components.

Sources:

  • Ming, Lim Lai; Samsudin, Zambri Bin. Apparatus, System, And Method Of Providing A Ramped Interconnect For Semiconductor Fabrication. U.S. Patent Application Number 20250308956, filed December 18, 2024 and posted October 2, 2025. Patent URL (for desktop use only): https://ppubs.uspto.gov/pubwebapp/external.html?q=(20250308956)&db=US-PGPUB&type=ids