Patent Application Seeks to Reduce Floating Body Effect in N-Type MOSFET Devices

Strategic Insights -

Researchers from the US have proposed a novel solution to reduce the floating body effect (FBE) in N-type metal-oxide-semiconductor field-effect transistors (MOSFETs). The invented technology aims to mitigate the FBE, which can lead to increased current consumption and device degradation. The patent application, filed on April 10, 2024, describes an extended drain metal-oxide-semiconductor (EDMOS) FET device that incorporates a source-side structure with a Vbi reduction material (VRM) layer. This design enables significantly freer movement of holes from the body of the device towards the source region, thus reducing the FBE.

Key Takeaways:

  • The patent application aims to address the floating body effect (FBE) in N-type MOSFET devices, which can lead to increased current consumption and device degradation.
  • The invented technology proposes an extended drain metal-oxide-semiconductor (EDMOS) FET device that incorporates a source-side structure with a Vbi reduction material (VRM) layer.
  • The VRM layer reduces the built-in voltage Vbi of the device, allowing for significantly freer movement of holes from the body of the device towards the source region.
  • The device can be fabricated using a variety of materials, including germanium, silicon germanium alloy, and indium arsenide alloy.
  • The proposed device can be used in high-voltage applications, such as laptop computers, mobile telephones, and electric cars.
  • The inventors, Waleed Asadi, Nijita Kesavan, Sonja Nedeljkovic, and Jagar Singh, have filed the patent application on April 10, 2024, and it has been posted online on October 16, 2025.
  • The device can have a thin channel region and abutting thick edge regions, which can help to reduce the FBE.
  • The proposed method of fabrication includes forming a body region, a source region, a drift region, and a drain region within a semiconductor active layer.

Statistics:

  • The patent application was filed on April 10, 2024.
  • The patent application has been posted online on October 16, 2025.
  • The inventors have proposed an extended drain metal-oxide-semiconductor (EDMOS) FET device that incorporates a source-side structure with a Vbi reduction material (VRM) layer.
  • The VRM layer reduces the built-in voltage Vbi of the device, allowing for significantly freer movement of holes from the body of the device towards the source region.
  • The proposed device can be used in high-voltage applications, such as laptop computers, mobile telephones, and electric cars.

Sources:

  • Asadi, Waleed; Kesavan, Nijita; Nedeljkovic, Sonja; Singh, Jagar. Reduction of the Floating Body Effect in N-Type MOSFET Devices. U.S. Patent Application Number 20250324749, filed April 10, 2024 and posted October 16, 2025. Patent URL (for desktop use only): https://ppubs.uspto.gov/pubwebapp/external.html?q=(20250324749)&db=US-PGPUB&type=ids