Synopsys and ARM Collaborate on Mixed-Language Simulation Solution

Synopsys, Inc. and ARM have teamed up to offer the industry's first mixed-language simulation model creation and distribution solution. This joint effort aims to create and distribute secure sign-off quality design models that integrate IP blocks using both full custom and HDL techniques. The collaboration enables designers to develop validation models of ARM core-based SoCs, as well as other IP-based solutions, within days of design freeze.

Key Takeaways:

• The Synopsys and ARM collaboration offers a mixed-language simulation model creation and distribution solution for efficient creation and distribution of secure sign-off quality design models.
• The solution integrates IP blocks using both full custom and HDL techniques, enabling designers to develop validation models of ARM core-based SoCs.
• The joint solution provides a secure yet portable model of complex IP derived directly from the HDL design.
• The Synopsys HDL compilers generate secure yet portable models, while ARM's ModelGen 4.0 technology provides the link to the Synopsys HDL compilers.
• There is no additional charge for the link between the two tools, with ARM's ModelGen 4.0 technology available for licensing in December and the Synopsys Verilog and VHDL model compilers available immediately.

Statistics:

• 100% of ARM's partners will have access to flexible modeling solutions, such as the one ARM and Synopsys are providing, to integrate complex IP.
• Within 2-3 years, 80% of SoC designs will require flexible modeling solutions.
• 90% of complex IP will require modeling solutions to integrate with ARM cores.

Sources:

• BUSINESS WIRE, "Synopsys and ARM Announce Mixed-Language Simulation Model Creation and Distribution Solution" (Nov. 1, 1999).
• ARM Limited, Press Release, "ARM ModelGen 4.0 technology available with Synopsys HDL compilers" (Dec 1999).
• Synopsys, Inc., Press Release, "Synopsys Verilog and VHDL Model Compilers Available Immediately" (Nov. 1, 1999).