Systems and Methods for Reducing Power at System-On-Chip

Strategic Insights -

Patent number 9026828, filed on December 31, 2012, and published online on May 5, 2015, proposes innovative systems and methods for reducing power consumption at system-on-chip. The invention, attributed to inventor Park, Jinkwon, focuses on optimizing power management in low-power systems, addressing the increasing need for energy conservation in home appliances and office equipment. This breakthrough incorporates low-power techniques, such as static and dynamic power consumption reduction, to minimize power consumption while maintaining operational efficiency.

Key Takeaways:

  • The patent, titled "Systems and Methods for Reducing Power at System-On-Chip," presents an inventive concept that includes a power-off domain block and a power-on domain block.
  • The power-off domain block receives power in response to the wake-up operation and comprises a main CPU, a memory controller, and various intellectual properties that perform individual functions.
  • The power-on domain block analyzes externally transferred data during a power-down state of the power-off domain block and substitutes an operation of the power-off domain block based on the analyzed result.
  • The inventive concept encompasses various aspects, including the power-off domain block being powered down in a power-save mode and the low-power management module performing an operation of the main CPU during the power-down state.
  • The wake-up intellectual property analyzes data, and the keep-alive intellectual property activates power of the power-off domain block according to the result analyzed by the wake-up intellectual property.
  • The system-on-chip also includes a power-on domain block with a low-power CPU and a memory that serves as an auxiliary memory of the power-off domain block at a power-on mode and as a memory storing programs and data for the low-power CPU at a power-off mode.
  • The power-on domain block analyzes externally transferred data during a power-down state of the power-off domain block to substituted an operation of the power-off domain block, based on the analyzed result.
  • When the system-on-chip satisfies a power-down condition, programs and data to be used by the low-power CPU are copied to the memory of the power-on domain block, the power-off domain block is powered down, and the low-power CPU is booted up.

Statistics:

  • The patent was filed on December 31, 2012, and published online on May 5, 2015.
  • The assigned patent number is 9026828.
  • The assignee for this patent is Samsung Electronics Co., Ltd. (KR).
  • The inventive concept addresses the need for energy conservation in home appliances and office equipment.
  • The systems and methods proposed in this patent aim to reduce power consumption at system-on-chip.

Sources:

  • Park, Jinkwon. Systems and Methods for Reducing Power at System-On-Chip. U.S. Patent Number 9026828, filed December 31, 2012, and published online on May 5, 2015. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9026828.PN.&OS=PN/9026828RS=PN/9026828
  • News reporting originating from Alexandria, Virginia, by VerticalNews journalists.