Toshiba Granted Patent for Semiconductor Memory Device

Toshiba has been assigned a patent for a "semiconductor memory device with sense circuit connected to sense node coupled to bit line," developed by Keiichi Kushida. This innovation aims to improve the functionality of semiconductor memory devices by enhancing the interaction between the sense circuit and the sense node. The patent application was filed on December 11, 2008, and was assigned the patent number 8,000,130.

Key Takeaways:

The patented device comprises a word line, a bit line, a memory cell, and a sense circuit connected to a sense node coupled to the bit line.
The sense circuit includes four transistors of different conduction types, which are activated by control signals to facilitate the reading of data stored in the memory cell.
The patented device allows for the efficient and accurate reading of data stored in the memory cell, enabling improved performance and functionality in semiconductor memory devices.
The patent application was filed by Toshiba on December 11, 2008, and was assigned the patent number 8,000,130.
The full-text of the patent is available on the U.S. Patent and Trademark Office's website, accessible via the provided link.
Keiichi Kushida is credited as the inventor of the patented device, and Toshiba has been assigned the patent for the semiconductor memory device.

Statistics:

The patent number assigned to the patented device is 8,000,130.
The patent application was filed on December 11, 2008.
The patented device comprises four transistors of different conduction types.
The sense circuit is activated by control signals given to the control signal line.
The full-text of the patent is available on the U.S. Patent and Trademark Office's website.

Sources:

U.S. Patent and Trademark Office - patent 8,000,130
http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=80,00,130.PN.&OS=PN/80,00,130&RS=PN/80,00,130