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Electronic components

Patent Application for Persisting Error Information Between Integrated Circuit Verification Checks

Strategic Insights

— 2 min read

A patent application filed by four inventors, including Michael Alexander Bowen and Frank Malgioglio, seeks to improve the efficiency of the design process for complex integrated circuits. The application, titled "Persisting Error Information Between Integrated Circuit Verification Checks," aims to leverage verification tools to enable error information to be persisted between iterations of a verification checking process and shared among design teams.

The inventors describe a technique where a verification tool performs a first verification checking run on an integrated circuit design under test (IC DUT) and generates an error report including an error entry for an error detected in the first verification checking run. Based on user input, the error entry is annotated with user-generated error information, which is then persisted between verification checking runs. The application also includes claims for a program product, a data processing system, and a method of data processing, all of which involve persisting error information in a similar manner.

The patent application has significant implications for the field of integrated circuit design, where verification tools play a crucial role in ensuring the accuracy and efficiency of the design process. By enabling error information to be persisted and shared among design teams, the proposed technique can help streamline the design process and reduce the likelihood of errors.

Key Takeaways:

  • The patent application proposes a technique for persisting error information between integrated circuit verification checks.
  • The technique involves annotating error entries with user-generated error information, which is then persisted between verification checking runs.
  • The application includes claims for a program product, a data processing system, and a method of data processing, all of which involve persisting error information.
  • The proposed technique has significant implications for the field of integrated circuit design, where verification tools play a crucial role in ensuring the accuracy and efficiency of the design process.
  • The inventors' technique can help streamline the design process and reduce the likelihood of errors.
  • The patent application was filed on April 11, 2024, and posted for public review on October 16, 2025.
  • The application was filed by Michael Alexander Bowen, Frank Malgioglio, Amanda Christine Venton, and David Wolpert.
  • The proposed technique involves using verification tools to improve the efficiency of the design process for complex integrated circuits.
  • The inventors' technique can help enable collaboration among design teams and reduce the likelihood of errors.

Statistics:

  • 1. The patent application includes 18 claims, covering a variety of aspects of the proposed technique.
  • 2. The application was filed by four inventors, including Michael Alexander Bowen, Frank Malgioglio, Amanda Christine Venton, and David Wolpert.
  • 3. The patent application has significant implications for the field of integrated circuit design.
  • 4. The proposed technique can help streamline the design process and reduce the likelihood of errors.
  • 5. The patent application was filed on April 11, 2024, and posted for public review on October 16, 2025.

Sources:

  • Bowen, Michael Alexander; Malgioglio, Frank; Venton, Amanda Christine; Wolpert, David. Persisting Error Information Between Integrated Circuit Verification Checks. U.S. Patent Application Number 20250322130, filed April 11, 2024 and posted October 16, 2025. Patent URL (for desktop use only): https://ppubs.uspto.gov/pubwebapp/external.html?q=(20250322130)&db=US-PGPUB&type=ids

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