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Analogy Introduces VeriasHDL: A Game-Changing Tool for Mechatronics Design

Strategic Insights

— 2 min read

Analogy, Inc. has introduced VeriasHDL, the first multi-language software design tool that combines analog, digital, mechanical, and hydraulic analyses in developing and testing mechatronics systems. This innovative tool is a key component of Analogy's TheHDL open simulation environment, designed to facilitate the design of mechatronics systems. VeriasHDL is built around VHDL-AMS, the recently approved open software language standard developed by the Institute of Electrical and Electronics Engineers (IEEE). The tool's unique "single kernel simulator" allows for interoperability with future model libraries and co-simulation with hardware description languages such as Verilog, VHDL, Verilog-AMS, MAST(R), Spice, and VHDL-AMS.

Key Takeaways:

  • VeriasHDL is the first multi-language software design tool that combines analog, digital, mechanical, and hydraulic analyses for mechatronics systems.
  • The tool uses the VHDL-AMS language standard developed by the IEEE.
  • VeriasHDL is a part of Analogy's TheHDL open simulation environment for mechatronics design.
  • The tool's "single kernel simulator" enables interoperability with future model libraries and co-simulation with various hardware description languages.
  • VeriasHDL was created to address the need for standardization in tools for mechatronic systems design.
  • Analogy aims to reduce the complexity of mixed-technology design and simulation with VeriasHDL.
  • The company believes that the use of top-down techniques is essential for designing mechatronic applications.
  • The integration of mechanical, electrical, and electronic systems in vehicles has driven the need for a tool like VeriasHDL.
  • The tool's development has been influenced by the IEEE standard, system-on-chip design, and the need for mixed-signal and mixed-technology design.
  • Analogy's TheHDL open simulation environment is addressing the forces driving the need for a tool like VeriasHDL.

Statistics:

  • The automotive industry took over two decades to integrate mechanical CAD, CAM, and CAE tools.
  • The integration of simulators for mixed technologies using VeriasHDL is expected to reduce the number of software tools required for systems analysis by an unspecified amount.
  • Training time and cost are expected to be reduced by an unspecified amount with the use of VeriasHDL.
  • VeriasHDL is the first single kernel simulator to provide the full range of system, behavioral, digital, and analog capabilities for mixed-technology design and simulation.

Sources:

  • Beaverton, Ore., June 29 /PRNewswire/: Analogy, Inc. (Nasdaq: ANLG) today introduced VeriasHDL(TM), the automotive industry's first multi-language software design tool...
  • Analogy, Inc. is a world leader in the development of high-performance design and analysis software and model libraries for the design of mixed-signal and mixed-technology systems.

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