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Integrated circuit fabrication

Breakthrough in Semiconductor Manufacturing: Powerchip Semiconductor Patent Application

Strategic Insights

— 2 min read

Powerchip Semiconductor Manufacturing Corporation has recently filed a patent application for a novel semiconductor manufacturing method that aims to improve the electrical performance of semiconductor devices. The invention, credited to Lin, Meng-Han, proposes a new approach to manufacturing that addresses the issue of uneven gate dielectric layer thickness, which can reduce the breakdown voltage of high-voltage transistor devices.

The proposed method involves forming a semiconductor layer in a substrate, then removing a portion of the semiconductor layer and a portion of the substrate to create a trench. An isolation structure is formed in the trench, and the semiconductor layer is removed to create a first recess in the substrate. A gate dielectric layer is then formed on the substrate exposed by the first recess, ensuring a uniform thickness and enhanced electrical performance.

This innovative approach has been detailed in a 20-claim patent application, filed on April 24, 2024, and made available online on October 2, 2025. The application showcases various embodiments of the invention, each highlighting specific aspects of the manufacturing method. These embodiments demonstrate the flexibility and adaptability of the invention, making it a promising solution for semiconductor manufacturers seeking to improve their product quality and efficiency.

Key Takeaways:

  • The patent application describes a novel semiconductor manufacturing method that addresses the issue of uneven gate dielectric layer thickness.
  • The method involves forming a semiconductor layer in a substrate, then removing a portion of the semiconductor layer and a portion of the substrate to create a trench.
  • An isolation structure is formed in the trench, and the semiconductor layer is removed to create a first recess in the substrate.
  • A gate dielectric layer is then formed on the substrate exposed by the first recess, ensuring a uniform thickness and enhanced electrical performance.
  • The invention has been detailed in a 20-claim patent application, filed on April 24, 2024.
  • The application highlights various embodiments of the invention, demonstrating its flexibility and adaptability.
  • The innovative approach has the potential to improve the electrical performance of semiconductor devices and reduce production costs.

Statistics:

  • 20 claims in the patent application describe the novel semiconductor manufacturing method.
  • The invention has been filed by Powerchip Semiconductor Manufacturing Corporation.
  • The patent application was made available online on October 2, 2025.
  • 5 embodiments of the invention have been detailed in the patent application.
  • The manufacturing method involves 7 processing steps.
  • The gate dielectric layer's uniform thickness is critical for enhanced electrical performance.

Sources:

  • Lin, Meng-Han. Manufacturing Method Of Semiconductor Structure. U.S. Patent Application Number 20250311385, filed April 24, 2024 and posted October 2, 2025. Patent URL (for desktop use only): https://ppubs.uspto.gov/pubwebapp/external.html?q=(20250311385)&db=US-PGPUB&type=ids

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