Cadence Introduces Analog EDA Tools Complying with OVI 1.0 Verilog-A

Cadence Design Systems, Inc. has introduced new analog EDA tools that comply with OVI 1.0 Verilog-A, an analog extension to the industry-standard Verilog hardware description language (HDL). The tool suite, which includes the industry's first Verilog-A compliant debugger, is designed to make the process of analog design easier and more automated, aiming to reduce the complexity and manual methodology associated with traditional HDLs.

Key Takeaways:

• The Cadence tool suite is a complete development solution that includes an analog HDL-based compiler, a scripting language for model characterization and testing, and a Verilog-A compliant debugger.
• The Verilog-A compliant debugger automatically checks probes, break points, and inspects model parameters to ensure circuits match their models.
• The scripting language queues up testbenches to characterize the model further.
• Analog designers use the Verilog-A language to describe their design, similar to a standard VHDL or Verilog HDL design flow.
• The design flow is intended to make analog design easier and more automated.
• Analog design is becoming increasingly important as the industry moves towards system on silicon design.
• Open standards like Verilog-A are key to tool interoperability.

Statistics:

• The Verilog-A compliant development solution is now available in volume and operates on UNIX-based workstations.
• Prices start at $20,000.
• Cadence has over 3,750 employees and annual sales of $916 million in 1997.
• The company is headquartered in San Jose, Calif. and traded on the New York Stock Exchange under the symbol CDN.

Sources:

• Cadence Design Systems, Inc. press release, March 2, 1998.
• OVI's Technical Coordinating Committee website.
• Cadence Design Systems, Inc. website.