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Freescale Semiconductor Awarded Patent for Anti-Stiction Dimple Formation Method

Strategic Insights

— 1 min read

Freescale Semiconductor has been granted a patent for its innovative method of anti-stiction dimple formation under Microelectromechanical Systems (MEMS). The patent, developed by Woo Tae Park and Hemant D. Desai, addresses the challenge of reducing stiction between MEMS structures and their substrates. By creating a method to form dished portions of semiconductor material within recesses, Freescale's approach enables the development of more efficient MEMS transducers.

Key Takeaways:

  • The patented method involves patterning recesses in a dielectric layer overlying a substrate, followed by the formation of a conformal layer of semiconductor material.
  • The conformal layer is then chemically mechanically polished to create dished portions of semiconductor material within the recesses.
  • Each dished portion has a depth proximate to its central portion that is less than the thickness of the semiconductor material proximate to its outer portion.
  • The semiconductor wafer is bonded to the polished surface, and then patterned with openings according to the requirements of a desired MEMS transducer.
  • The resulting MEMS transducer is released, advantageously exposing anti-stiction features formed from the outer edges of the dished portion of semiconductor material.
  • The patent application was filed on October 31, 2007, as 11/932,099.
  • The full-text of the patent is available on the USPTO website at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.htm&r=87&f=G&l=50&d=PTXT&s1=20110405.PD.&s2=(TX.ASST.)&co1=AND&p=2&OS=ISD/04/05/2011+AND+AS/TX&RS=ISD/04/05/2011+AND+AS/TX

Statistics:

  • Patent number: 7,919,006
  • Application date: October 31, 2007
  • Patent application number: 11/932,099
  • Full-text of the patent available on the USPTO website: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.htm&r=87&f=G&l=50&d=PTXT&s1=20110405.PD.&s2=(TX.ASST.)&co1=AND&p=2&OS=ISD/04/05/2011+AND+AS/TX&RS=ISD/04/05/2011+AND+AS/TX

Sources:

  • Freescale Semiconductor's patent for "method of anti-stiction dimple formation under MEMS" (Patent number: 7,919,006)
  • US Patent and Trademark Office (USPTO)
  • Patent application number: 11/932,099
  • Patent Abstract on USPTO website
  • Freescale Semiconductor's press release (no specific date mentioned in the original text)

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