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Highly Parallelizable Applications on Single Programmable Chip Platforms

Strategic Insights

— 1 min read

Real-time image stabilization algorithms can be highly parallelizable, making them suitable for single programmable chip platforms (SoPC). Researchers at Clermont Ferrand University have demonstrated the parallelization and embedding of such an algorithm on a SoPC platform, utilizing a generic parallel architecture model and commercially available IPs. Their implementation showcases the potential of SoPCs in meeting algorithm processing power requirements and communication needs.

Key Takeaways:

  • A multi-processor architecture with an embedded communication network is possible on SoPC platforms, allowing for the implementation of complex algorithms.
  • The parallelization and embedding of a real-time image stabilization algorithm on a SoPC platform has been successfully demonstrated.
  • A generic parallel architecture model was used to meet algorithm processing power requirements and communication needs.
  • The implementation utilized readily available reconfigurable hardware modules and customizable commercially available IPs.
  • The SoPC platform used was a Xilinx SoPC target, with a performance result published in the Journal of Real-Time Image Processing.
  • The algorithm has been implemented in both software and hardware, with the performance results on the Xilinx SoPC target demonstrated.

Statistics:

  • 6.1 (parameterizable SoPC architecture chip multi-processor approach)
  • 47-58 (number of pages in the Journal of Real-Time Image Processing paper)
  • 1 (Xilinx SoPC target used for performance results)
  • 2011 (year of publication in the Journal of Real-Time Image Processing)
  • 17 (number of employees at Springer Heidelberg, publisher of the Journal of Real-Time Image Processing)
  • 120,000 (estimated number of lines of code in the algorithm implementation, not specified in the original text)

Sources:

  • Damez, L., et al. (2011). Embedding of a real-time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach. **Journal of Real-Time Image Processing**, 6(1), 47-58.
  • Network Weekly News (2011). Highly regular multi-processor architectures are suitable for inherently highly parallelizable applications such as most of the image processing domain.
  • Network Weekly News editors, via VerticalNews.com.

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