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IBM Assigned Patent for Selective Implementation of Barrier Layers in CMOS Device Fabrication

Strategic Insights

— 1 min read

International Business Machines, Armonk, N.Y., has been assigned a patent developed by ten co-inventors for a "selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics." The patent, assigned the number 7,928,514, was developed by Nestor A. Bojarczuk Jr., Cyril Cabral Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, and Vamsi K. Paruchuri. The patent provides a semiconductor structure for improving CMOS device fabrication with high-k dielectrics, including a first gate stack for pFET devices and a second gate stack for nFET devices. The innovation aims to stabilize threshold voltage and flatband voltage of the p-FET device.

Key Takeaways:

  • The patent 7,928,514 was developed by ten co-inventors at International Business Machines, including Nestor A. Bojarczuk Jr., Cyril Cabral Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, and Vamsi K. Paruchuri.
  • The patent provides a semiconductor structure including a first gate stack for pFET devices and a second gate stack for nFET devices, both using high-k gate dielectrics.
  • The insulating interlayer in the first gate stack includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device.
  • The insulating interlayer is created using one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride, and indium oxynitride.
  • The patent application was filed on Jan. 16, 2009, with application number 12/355,368.

Statistics:

  • The patent number is 7,928,514.
  • The patent was developed by ten co-inventors.
  • The invention applies to CMOS device fabrication with high-k dielectrics.
  • The first gate stack includes a high-k gate dielectric, an insulating interlayer, and a fully silicided metal gate electrode.
  • The insulating interlayer includes one of seven different metal nitrides.
  • The patent application was filed on Jan. 16, 2009.

Sources:

  • "U.S. Patent and Trademark Office." PatFT Search: 7,928,514, 2011.
  • "International Business Machines." IBM Assigned Patent for Selective Implementation of Barrier Layers, April 21, 2011.

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