IBM Develops Novel CMOS Structure with III-V and Silicon-Germanium Transistors

Researchers at International Business Machines Corporation (IBM) have developed a novel CMOS (Complementary Metal-Oxide-Semiconductor) structure that integrates III-V (Indium-Gallium-Arsenide) n-channel field effect transistors and silicon-germanium p-channel field effect transistors on insulator. This innovative design aims to overcome the scaling limitations of traditional silicon-based CMOS technology and achieve higher performance and efficiency.

The IBM team, led by inventors Cheng, Cheng-wei, Majumdar, Amlan, and Shiu, Kuen-Ting, has filed a patent application for the novel CMOS structure, which comprises a NFET (n-channel field effect transistor) and a PFET (p-channel field effect transistor) formed on a wafer. The channels of both transistors include semiconductor material formed on III-V semiconductor material, which acts as a buried oxide due to a valence band offset.

The CMOS structure is designed to improve device switching speed and reduce power consumption. The III-V n-channel field effect transistors provide enhanced electron transport properties, while the silicon-germanium p-channel field effect transistors enhance hole transport properties. This combination enables the creation of high-performance and low-power CMOS-based circuits and chips.

Key Takeaways:

• The novel CMOS structure integrates III-V n-channel field effect transistors and silicon-germanium p-channel field effect transistors on insulator, aiming to overcome the scaling limitations of traditional silicon-based CMOS technology.
• The design combines enhanced electron transport properties from III-V n-channel field effect transistors with superior hole transport properties from silicon-germanium p-channel field effect transistors.
• The CMOS structure is fabricated using a multi-step process, with a total of 14 sequences of fabrication steps.
• The IBM team has developed a detailed patent specification, including 14 figures, to illustrate the fabrication process and the CMOS structure.
• The invention aims to improve device switching speed and reduce power consumption in CMOS-based circuits and chips.

Statistics:

• The CMOS structure is designed for use in the 10 nm gate length regime.
• The III-V n-channel field effect transistors provide enhanced electron transport properties compared to silicon n-channel field effect transistors.
• Silicon-germanium p-channel field effect transistors offer superior hole transport properties compared to silicon p-channel field effect transistors.
• The CMOS structure consists of a NFET and a PFET, both with a channel length of 10 nm.
• The total number of fabrication steps required to create the CMOS structure is 14.

Sources:

• Cheng, Cheng-wei; Majumdar, Amlan; Shiu, Kuen-Ting. Complementary Metal-Oxide-Semiconductor Structure with Iii-V and Silicon Germanium Transistors on Insulator. Filed March 6, 2014 and posted September 17, 2015. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=1867&p=38&f=G&l=50&d=PG01&S1=20150910.PD.&OS=PD/20150910&RS=PD/20150910