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IBM Patented Lattice-Mismatched Semiconductor Layer Structure for Enhanced Device Performance

Strategic Insights

— 1 min read

International Business Machines (IBM) has been assigned a patent (7,994,028) for a novel semiconductor layer structure that enables the development of high-performance devices. The patent, developed by Tymon Barwicz and Devendra K. Sadana, describes a method for manufacturing a semiconductor substrate with a single crystalline group IV semiconductor layer and a lattice-mismatched group IV semiconductor alloy layer.

This innovative structure allows for the simultaneous growth of group IV semiconductor devices, such as silicon devices, and compound semiconductor devices, such as GaAs devices with laser emitting capabilities, on the same lithographic level. The lattice mismatched group IV semiconductor alloy layer is epitaxially grown on a portion of the semiconductor layer while another portion is masked, enabling the tuning of its composition to match the lattice constant of a single crystalline compound semiconductor layer.

The patent application was filed on August 10, 2009 (12/538,759), and the full-text of the patent is available online. This breakthrough technology has significant implications for the development of high-performance electronic devices and could potentially lead to advancements in various fields, including computing, communication, and optoelectronics.

Key Takeaways:

  • IBM has been assigned a patent (7,994,028) for a novel semiconductor layer structure with lattice-mismatched single-crystalline semiconductor layers.
  • The patent was developed by Tymon Barwicz and Devendra K. Sadana and enables the simultaneous growth of group IV semiconductor devices and compound semiconductor devices on the same lithographic level.
  • The lattice mismatched group IV semiconductor alloy layer is tuned to match the lattice constant of a single crystalline compound semiconductor layer.
  • The structure allows for the formation of high-performance devices with enhanced capabilities.
  • The patent application was filed on August 10, 2009 (12/538,759).

Statistics:

  • Patent number: 7,994,028
  • Filing date: August 10, 2009 (12/538,759)
  • Number of semiconductor layers involved: 2 (single crystalline group IV semiconductor layer and lattice-mismatched group IV semiconductor alloy layer)

Sources:

  • U.S. Patent and Trademark Office (http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,994,028.PN.&OS=PN/7,994,028&RS=PN/7,994,028)

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