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Computer peripherals industry

Motorola Announces Integrated Level Two Cache Solution for PowerPC Systems

Strategic Insights

— 1 min read

Motorola's Microprocessor and Memory Technologies Group has unveiled a new integrated Level Two (L2) cache solution for PowerPC computer systems. The MPC2604GA integrates standard cell logic technology with Motorola's high-speed SRAM core memory to reduce chip count and boost performance. This integrated 4-way set associative look-aside cache with copy-back or optional write-through capability provides a two- or four-chip L2 cache solution for the 64-bit PowerPC microprocessor bus. The MPC2604GA can perform 2-1-1-1 bursts at 66MHz, outpacing discrete solutions.

Key Takeaways:

  • The MPC2604GA integrates standard cell logic technology with Motorola's high-speed SRAM core memory, reducing chip count and boosting performance.
  • The integrated 4-way set associative look-aside cache with copy-back or optional write-through capability provides a two- or four-chip L2 cache solution for the 64-bit PowerPC microprocessor bus.
  • The MPC2604GA can perform 2-1-1-1 bursts at 66MHz, outpacing discrete solutions.
  • The integrated cache solution offers several advantages for customers, including reduced processor bus loading and minimized read miss penalty.
  • The MPC2604GA utilizes Motorola's popular 0.5 micron BiCMOS fast SRAM, organized in a 32K x 36 array, as the data memory core.
  • The cache controller ensures all components of the L2 cache communicate properly and determines the types of transactions occurring on the bus.
  • The MPC2604GA is specifically designed for use with PowerPC 604, PowerPC 603, and PowerPC 601 microprocessor-based systems and supports the PowerPC 604 microprocessor's fast L2 mode.
  • The integrated cache, packaged in a high board density 25mm plastic ball grid array (PBGA), will be available for general sampling in the first quarter of 1996.

Statistics:

  • The MPC2604GA can perform 2-1-1-1 bursts at 66MHz.
  • The integrated cache solution offers a reduction in chip count by 2-4 compared to discrete solutions.
  • The MPC2604GA has a 32K x 36 array data memory core.
  • The cache controller ensures all components of the L2 cache communicate properly.
  • Production of the MPC2604GA is scheduled to begin in the second quarter of 1996.
  • Pricing for the MPC2604GA is expected to be $58 each in 1,000 piece quantities.

Sources:

  • Motorola
  • International Business Machines Corporation
  • Motorola Media Relations, P.O. Box 52073, M/D 56-102, Phoenix, AZ 85072
  • Editorial: Gordy Davies of Motorola, 512-505-8823 or gordy_davies@oakqm3.sps.mot.com
  • Reader: Fast Static RAM Marketing, 512-933-7726

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