Stressed Nanowire Stack for Field Effect Transistor Improves Semiconductor Performance

A patent application by inventors Martin M. Frank, Pouya Hashemi, Ali Khakifirooz, and Alexander Reznicek, filed on March 21, 2014, and available online on October 1, 2015, has shed light on a novel approach to improve semiconductor performance. The invention revolves around a stressed nanowire stack for a field effect transistor, addressing a significant challenge in the field. The inventors emphasize the need to retain mechanical stress in suspended semiconductor nanowires to achieve high performance in field effect transistors.

Key Takeaways:

• The invention describes a semiconductor structure comprising a first semiconductor nanowire, a second semiconductor nanowire, and a gate structure surrounding both nanowires.
• The gate structure includes a first gate dielectric and a second gate dielectric, which differ in composition or thickness, to alleviate stress in the nanowires.
• A method of forming the semiconductor structure involves patterning an alternating stack of disposable material portions and semiconductor material portions, followed by the removal of the disposable material portions and the formation of isolated gate structures.
• A disposable gate structure is used to prevent distortion of the suspended semiconductor nanowires during the formation of the field effect transistor.
• The replacement of the disposable gate structure with a replacement gate structure, including a second gate dielectric, a second metallic gate electrode portion, and a second semiconductor gate electrode portion, is also described.
• Various embodiments of the invention are illustrated through figures showing the top-down and cross-sectional views of the semiconductor structure at different stages of fabrication.
• The inventors highlight the advantages of the stressed nanowire stack in providing a high-performance field effect transistor.

Statistics:

• The patent application has 14 figures illustrating the various stages of semiconductor structure fabrication.
• The invention uses a combination of first and second gate dielectrics with different compositions or thickness to alleviate stress in suspended semiconductor nanowires.
• The disposable gate structure prevents distortion of the semiconductor nanowires during fabrication, ensuring high performance in the field effect transistor.
• The replacement gate structure includes a second gate dielectric, a second metallic gate electrode portion, and a second semiconductor gate electrode portion.

Sources:

• Frank, Martin M.; Hashemi, Pouya; Khakifirooz, Ali; Reznicek, Alexander. Stressed Nanowire Stack for Field Effect Transistor. Filed March 21, 2014 and posted October 1, 2015. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=1639&p=33&f=G&l=50&d=PG01&S1=20150924.PD.&OS=PD/20150924&RS=PD/20150924