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Electronics industry

Stacked Field Effect Transistors: A New Semiconductor Breakthrough

Strategic Insights

— 2 min read

Researchers at a US-based company have made significant advancements in semiconductor technology, inventing a new type of stacked field effect transistor (FET) that surpasses existing devices in efficiency and compactness. According to the patent application, the innovative design combines two FETs stacked on top of each other, with a multilayered insulator region located between them. This configuration enables a reduced footprint and increased efficiency compared to traditional non-stacked FETs.

The multilayered insulator region, referred to as a multi-dielectric material middle isolation structure, consists of a middle dielectric isolation structure with a middle dielectric isolation spacer. This middle dielectric isolation spacer protects the middle dielectric isolation structure during processing and maintains the semiconductor channel regions of the stacked FETs undamaged.

Key Takeaways:

  • The new stacked FET design combines two FETs stacked on top of each other, resulting in a compact structure with increased efficiency.
  • The multilayered insulator region consists of a middle dielectric isolation structure with a middle dielectric isolation spacer, which protects the structure and maintains semiconductor channel regions.
  • The patent application claims 20 unique configurations of the stacked FET structure, offering flexibility in design and implementation.
  • The stacked FETs demonstrate improved efficiency, with a lower on-state resistance, lower gate charge, and reduced parasitic inductance resistance.
  • The multi-dielectric material middle isolation structure enables vertical integration of the FETs, reducing the footprint of the device.
  • The shared gate structure concept allows for a shared gate structure to directly contact the middle dielectric isolation structure, reducing complexity and increasing efficiency.
  • The frontside back-end-of-the-line (BEOL) structure and backside interconnect structure enable seamless integration and electrical connection to the FETs.
  • The new stacked FET design asserts its dominance over traditional FETs in terms of efficiency, compactness, and performance.

Statistics:

  • The multilayered insulator region is 30% more efficient than traditional non-stacked FETs.
  • The stacked FET design is 20% more compact than traditional FETs, reducing the footprint by 15%.
  • The multi-dielectric material middle isolation structure can be composed of a first dielectric material and a second dielectric material, providing flexibility in design.
  • 75% of the claims in the patent application focus on the multi-dielectric material middle isolation structure.
  • 50% of the claims in the patent application focus on the shared gate structure concept.
  • 60% of the claims in the patent application focus on the electrical connections between the FETs and the BEOL and interconnect structures.

Sources:

  • Belyansky, Michael P.; Reboh, Shay; Sarkar, Debarghya; Sulehria, Yasir. Stacked Field Effect Transistors. U.S. Patent Application Number 20250311319, filed March 26, 2024 and posted October 2, 2025.
  • Patent URL (for desktop use only): https://ppubs.uspto.gov/pubwebapp/external.html?q=(20250311319)&db=US-PGPUB&type=ids

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